IDK LOL

I have been studying a lot about SystemVerilog interfaces lately and how to put all the actual interface logic in them. Because right now, the accepted way is to program controllers for each side and just reusing that because protocols don't change and the internal architecture usually deploy similar internal communication structures so changing. I want to be able to just use tasks and functions on the modules using these interfaces. But then I am now thinking

• Has it been done already? My references might be outdated
• Is it worth doing? Haven't people settled on other solutions by now?
• Do I really want to do this? Aren't other fields also exciting and don't have this problem
• What would this change? How would it help the world or me

So I stopped just before trying to flatten out the whole interface because it would be a pain to do that.

Hope they fix it soon.